Design Verification Engineer

Responsibilities

• Hands on system-level and block-level verification.
• Development of test plans and coverage plans.
• Testbench development and execution using UVM or other advanced DV methodologies.
• Creation of verification infrastructure and flows.
• Leverage architecture models and emulation environments to help verify large AI network functionality on the design.
• Further responsibilities will depend on background and skills.

Requirements

• Bachelor’s, Master’s, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 3+ years of industry experience developing verification testbenches.
• Knowledge of verification methodologies.
• Knowledge of computer architecture.
• Understanding of Verilog, SystemVerilog, and UVM.
• Proven track record of first-pass silicon success.
• Strong communication skills, both written and spoken.