Physical Design Lead/Manager

Qualifications and Experience

• BSEE Required, MSEE Preferred
• 8+ years of experience of physical design in SOCs.
• 3+ years of experience in managing projects and leading teams.
• Hands-on expertise in all of the following areas: Floorplanning, Power planning, Implementation of UPF Methodology, Logic and clock tree synthesis, Placement , Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR
• Full chip/ top-level expertise in multiple chip tape-outs.
• Good understanding and experience in SCAN, BIST, and ATPG.
• Strong background in TCL/Perl/Python programming is a must.
• Expertise in double patterning process nodes is desirable. Experience with sub 40 nM nodes required
• Expertise in Cadence or Synopsys RTL-to-GDSII flow is preferred.

Expectations

• Do the FC Floor Plan and Layout
• Set up the EDA tools and develop the scripts
• Develop the UPF methodology
• Implement the Power, Clock Grid
• Generate the SDF files
• Do the DRC, ERC, LVS, SI and Cross talk checks, Do the DFM checks
• Tapeout the chip
• Manage and mentor the PD and custom layout team…