Senior RTL Design Engineer

Responsibilities

• Design and implement RTL for Mythic's next-generation AI processor.
• Contribute to the development of a novel digital dataflow architecture, including a sophisticated scheduling subsystem, high-performance interconnect fabric, and advanced DMA engines.
• Develop and optimize high-performance, low-power components such as datapaths, controllers, memory subsystems, and interconnects.
• Collaborate with architects and verification engineers to define microarchitecture and ensure functional correctness.
• Drive timing closure by working closely with synthesis and physical design teams.
• Participate in design reviews and contribute to improving RTL coding practices and methodologies.

Requirements

• Bachelor’s, Master’s, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 8+ years of industry experience in RTL design, microarchitecture, and architecture development.
• Solid understanding of computer architecture fundamentals (pipelines, caches, coherence, memory hierarchies).
• Hands-on experience with one or more of the following subsystems: scheduling fabrics, high-performance interconnects, DMA engines, memory controllers, or datapath/control logic.
• Proficiency in Verilog/SystemVerilog and industry-standard RTL coding guidelines.
• Familiarity with timing constraints, physical design considerations, and EDA flows.
• Hands-on experience with simulation, synthesis, linting, and static timing analysis tools.
• Strong problem-solving and communication skills with ability to work in cross-functional teams.

Preferred Qualifications

• Familiarity with network-on-chip (NoC) architectures.
• Expertise in low-power design techniques (clock gating, power gating, multi-voltage domains).
• Experience with timing closure in advanced technology nodes and collaboration with physical design teams.
• Strong skills in performance modeling and trade-off analysis (PPA optimization).
• Hands-on experience with emulation/FPGA prototyping for early RTL validation.
• Familiarity with AI, DSP, or other parallel compute architectures.
• Strong scripting ability (Python or similar) for design automation and productivity.