Compiler Engineer – MLIR / PyTorch Infrastructure

About the role

Join us in advancing the MLIR ecosystem at Mythic. You’ll help extend our existing high-level dialects and design a new hardware-aware low-level dialect, building conversion paths that bridge to our current IRs. Working closely with hardware engineers and ML developers, your work will expand interoperability with PyTorch and other frameworks, laying the groundwork for long-term innovation. The result: an MLIR-based stack that unifies hardware constraints with developer needs and accelerates adoption of modern ecosystems.

Here's what you will do

• Architect the migration of the existing compiler flow into MLIR, defining dialects, passes, and lowering strategies.
• Build conversion paths between MLIR and Mythic’s custom low-level IR to keep both flows operational during migration.
• Define validation infrastructure within MLIR, including interpretation or execution paths for simulation and debugging.
• Enable compilation by extending MLIR integration across analog accelerators and digital subsystems.
• Leverage Torch-MLIR where PyTorch inputs are available, and guide future integration with PyTorch 2.0 compiler technologies (TorchInductor, TorchDynamo, Torch-MLIR)

Here's the background we hope you will have

• 3+ years of experience in compiler or high-performance systems development.
• Proficiency in modern C++ (C++14/17/20) and Python.
• Direct, hands-on experience with MLIR, including dialect design, compiler passes, or lowering pipelines.
• Strong understanding of compiler IRs and transformations, with the ability to reason about lowering from high-level ops to hardware-aware representations.

The following would be nice to have, but is not required

• Experience architecting complete MLIR flows: from frontend dialects down to hardware-aware dialects, including conversion to and from existing IRs.
• Familiarity with PyTorch compiler technologies, especially Torch-MLIR and integration paths with PyTorch 2.0 (TorchDynamo, TorchInductor).
• Knowledge of dataflow architectures, scheduling, and memory orchestration.
• Background in heterogeneous or specialized accelerators (e.g., analog compute, NPUs, GPUs, DSPs).